A Low Power High PSR Wide Load LDO With Load-Dependent Feedforward Cancellation Technique

One of the most critical parameters of low drop-out regulators (LDOs) is the power supply rejection (PSR) over different frequencies [1]. We propose a low power LDO with a feed-forward load-dependent cancellation buffer (FFLCB) technique. The proposed LDO achieves a high PSR over a wide frequency range with low power and area consumption. The LDO is implemented in 65 nm CMOS technology and achieves a PSR better than 71 dB up to 10 MHz for output load currents up to 25 mA with a 4 µF output load cap. The design is suitable for LDOs with wide load current ranges up to 200 mA and load capacitor range from 1 nF to 12 µF. The proposed LDO consumes no-load quiescent current of 10 µA and area of 200 µm x 180 µm.