Gate Voltage Pulse Rising Edge Dependent Dynamic Hot Carrier Degradation in Poly-Si Thin-Film Transistors

Dynamic degradation becomes a critical issue for thin-film transistors (TFTs) used in emerging new displays driven by high frequency gate voltage
${V}_{\text {G}}$
pulses. In this study,
${V}_{\text {G}}$
pulse rising edge dependent dynamic hot carrier degradation of poly-Si TFTs is investigated. It is demonstrated that rising edge of
${V}_{\text {G}}$
pulses which swing within the OFF-state of TFTs causes the degradation, while that of normal
${V}_{\text {G}}$
pulses which switch between the ON and OFF states across the flat band voltage
${V}_{\text {FB}}$
of TFTs does not. Based on transient TCAD simulation, the underlying mechanism of rising edge dependent degradation is proposed, which is based on the non-equilibrium PN junction degradation model previously proposed to explain
${V}_{\text {G}}$
pulse falling edge dependent degradation of poly-Si TFTs. Hence, the dynamic degradation model of poly-Si TFTs related to both rising and falling edge of the
${V}_{\text {G}}$
pulses can be unified now, which is applicable to fast gate pulses with steep rising and/or falling edges in sub-
$\mu \text{s}$
level.