Silicon-on-Insulator Lateral DMOS With Potential Modulation Plates and Multiple Deep-Oxide Trenches

A silicon-on-insulator (SOI) lateral diffused metal-oxide semiconductor (LDMOS) with potential modulation plates (PMPs) and deep-oxide trenches (DOTs) is proposed and studied through TCAD simulations, which aims to enhance the electron mobility and improve the ON-resistance (
${R}_{ \mathrm{\scriptscriptstyle ON}}$
). The proposed SOI LDMOS consists of a conduction cell and an auxiliary cell. The surface electric potential in the conduction cell can be modulated by PMPs in both the ON-state and the OFF-state. In the ON-state, the gate voltage (
${V}_{G}$
) is delivered to the auxiliary cell and can be fully sustained by P-/N-well junction. Then, electrodes (
${P}1$
–
${P}15$
) arranged between the adjacent DOTs in the auxiliary cell deliver
${V}_{G}$
back to PMPs, which can effectively induce the electron accumulation on the silicon surface in the conduction cell. The enhanced electron accumulation in turn results in high electron mobility and low
${R}_{ \mathrm{\scriptscriptstyle ON}}$
. In the OFF-state, the electric field and potential are reshaped by DOTs and PMPs, ensuring a high breakdown voltage (BV). In addition, the maximum lattice temperature (
${T}_{\text {max}}$
) and temperature rise (
$ {\Delta } {T} = {T}_{\text {max}} -{T}_{\text {in}}$
,
${T}_{\text {in}}$
: initial temperature) can be significantly decreased. Compared with the conventional SOI LDMOS, the proposed SOI LDMOS achieves 43.29% reduction in
${R}_{ \mathrm{\scriptscriptstyle ON}}$
at
${V}_{G} =15$
V without deteriorating BV and 50% decrease in
$ {\Delta } {T} $
at
${I}_{\text {DS}} =0.2$
A (42 A/cm
$^{{2}}$
).