A new charge redistribution D/A and A/D converter technique - pseudo C-2C ladder

C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of C-2C ladder restrict the linearity of the DAC. In this paper, a pseudo C-2C ladder structure is proposed. It compensates for the parasitic effect by adjusting the capacitor values in the ladders according to an optimization algorithm with further adjustments possible via an adaptive calibration method. Using this technique, a 3.3 V 9.2 mW 12-bit 1.4 MSPS successive approximation ADC was implemented in an HP0.5 /spl mu/m single-poly triple-metal CMOS technology.