Very-low-power analog cells in CMOS

Low power supply consumption has become one of the main issues in the electronics industry for many product areas such as cellular telephones, portable personal computers and biomedical implants. The aim of this work is to investigate the main drawbacks involved in the design of CMOS analog cells biased in weak inversion. Biasing a cell in weak inversion makes it possible to achieve a power consumption that is one thousandth lower than common analog cells designed to operate in strong inversion. This work has involved the following subjects: a study of models for MOS transistors operating in weak inversion and strong inversion regions; a methodology to convert LEVEL 2 Spice model to EKV model; study of basic analog cell blocks suitable for low power mixed-mode IC design; design methodology for low power analog cells; comparison between these cells and some commercial ones; study of analog layout techniques.