Solving Power Integrity Challenges for Smart Computing Era

To solve increasingly difficult power delivery issue for high-end 2.5D and 3D based smart computing systems, we propose the combined structure of backside PDN and integrated stack capacitor (ISC). Transistor shrinkage continues to deliver the performance needs for AI-enabled smart devices with relatively constant device size causing the power delivery path to be very narrow and resulting a severe IR-drop issue. The concept of backside PDN has recently been proposed to minimize the delivery path and IR drop. To further address AC noise, we propose using backside PDN with ISC. To simplify the analysis, we model the system using a lumped circuit and simulate on both frequency and time domains. In the simulation, we assume the simplest current scenario which assumes step pulse after idle state. ISC can be integrated in 2.5D and 3D systems in three different ways: discrete device, 2.5D silicon interposer, 3D Wafer-on-Wafer (WoW) integration. Our simulation assumes interposer-based ISC with backside PDN for a variety of analysis. As confirmed in the previous researches related to ISC, hundreds of MHz noise is effectively decreased. Applying of backside PDN decreases the voltage drop at the steady state as well.