Simulation and experiment on warpage of heterogeneous integrated fan-out panel level package

Compared with fan-out wafer-level package (FOWLP), fan-out panel-level package (FOPLP) has the characteristics of high efficiency, low cost, and good electrical performance. However, the panel-level package panel will warp due to the shrinkage of the epoxy molding compound (EMC) during curing and the mismatch of the coefficient of thermal expansion (CTE) between the constituent materials in cooling and heating. For panels with larger size, the maximum warpage will increase, which will make the followed processes and handling more challenging. Heterogeneous integration refers to the combination of different chips through packaging technology, which can improve production efficiency and make the packaged chip more powerful, but the thermally induced warpage of the chip will be more complicated. In this work, we used a high-precision projection moire device with a maximum measuring range of 600mm×600mm to measure the warpage after heating of a 510mm×515mm fan-out panel-level package panel. The panel contains large chips of 7mm×7mm and small chips of 2mm×2mm, which are arranged in a matrix at a certain interval using chip-first die down process. The large chips and small chips in the panel are close to each other, while the same chips are far away. Based on the panel material, geometry, chip arrangement and process conditions, a finite element model was established using ABAQUS to simulate the panel-level package panel warpage after heating. The difference between the simulation result and the experimental result is only 0.023mm, and the error is only 6.4%. The simulated warpage results are in good agreement with the experimental results.