The Effect of Interface Traps at the Si/SiO₂ Interface on the Transient Negative Capacitance of Ferroelectric FETs

We theoretically investigated the effect of interface traps ( D
_it
) at the Si/SiO
₂
interface on the transient negative capacitance (NC) effect of the ferroelectric (FE) FETs. We used a metal/FE/interlayer/Si (MFIS) capacitor in series with a resistor to simulate the NC effect. Our simulation results show that appropriate D
_it
can further improve the subthreshold swing (SS) by tuning the mismatch of the switching rate between free charges ( Q
_f
) and polarization charges ( P). In addition, we also analyzed the impact of different circuit parameters on the device performance. The following device design can improve the SS characteristics: thicker FE layer, thinner interlayer (DE), lower external resistance, and larger viscosity coefficient.