Hardware Aspects of Parallel Neural Network Implementation

In this paper a parallel neural network architecture is proposed targeting efficient hardware implementation on low-resource devices. Following the introduction of the proposed technique, the novel concept is applied on two basic function approximation examples namely cos(x) and sin(x). Quantitative results are offered and discussed in terms of accuracy and hardware complexity. It is shown that the proposed technique achieves promising results when considering low-power and high-performance hardware implementations targeted to edge devices.