A 3 GS/s >55 dBFS SNDR Time-Interleaved RF Track and Hold Amplifier with >67 dBc SFDR up to 3 GHz in 22FDX

In this paper a high-linear 3GS/s 2x TI RF TaH circuit driven by a single wideband bulk-controlled input buffer is presented. The measured output buffered TaH reveals an SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling subsampling. The SNDR is above 55 dBFS, with an input bandwidth of 4.5 GHz. The extracted clock jitter is about 45 fs rms and does not limit the SNDR up to 3 GHz. Interleaving mismatches, such as offset, gain, and time-skew between both lanes are calibrated digitally off-chip using a 37-tap FIR filter. Active body biasing is used to improve the TaH bandwidth, settling performance, leakage, and therewith the overall power consumption. The CMFB takes advantage of the body bias control by using the bulk as an input. The total power consumption of the TaH including the clock buffer is only 178mW from a triple 2V/0.9 V/-0.8V supply.