A Gate-Driver Architecture with High Common-Mode Noise Immunity under Extremely High dv/dt

Wide bandgap (WBG) devices usually have much faster switching speed than that of the traditional silicon devices, which, however, may pose challenges to the design of the power loop and gate loop. Extensive research has been done to address the drain-source voltage overshoot and oscillation issues by reducing the power loop stray inductance. To further enable higher switching frequency, the issues on the gate driver side still need to be addressed. The crosstalk phenomenon on gate-source voltage, as one of the major issues, has attracted lots of attention and can be mitigated by various approaches. In addition, when dv/dt is extremely high, the common-mode (CM) noise may deteriorate the control signals through the capacitive coupling, which still need to be addressed, considering just 1.5V voltage noise can lead to false triggering on the PWM input of digital isolators. In this work, four gate driver architectures in the existing literature are studied and compared in terms of the CM noise immunity. LT-spice small-signal models are utilized for simulation studies to compare the CM noise immunity of different gate driver designs quantitatively. The prototype of the optimal design was built and experimentally tested using a 3.3 kV SiC MOSFET to validate its CM noise immunity under the extremely high dv/dt, even beyond 240 V/ns.