Reduced Parasitics Leading to a 99.2 % Efficient Single-Phase Nine-Level Inverter at a Switching Frequency of 800 kHz

The flying capacitor multilevel inverter is achieving highest power densities in recent power electronic devices. These positive results are based on minimal filter volumes due to effective output switching frequencies around hundreds of kilohertz up to several MHz. To achieve these high output frequencies the flying capacitor multilevel topology is crucial in addition with GaN switches. In theoretical calculations efficiencies around 99.4 % should be possible for the overall inverter at these operation conditions. These target efficiencies could not be reached yet in practical prototypes due to high commutation loop inductances and parasitic capacitances to the midpoint. This paper investigates the theoretical background of these parasitics, their effect on the inverter and presents an improved hardware implementation to verify the theoretical results. The presented hardware implementation of a single-phase inverter is using nine voltage levels and an effective output switching frequency of 800 kHz. The maximum reached peak efficiency of the overall inverter including an LCLC output filter is 99.2 % and a nominal power of 5 kW.