Machine Learning Based Prediction of Aging Caused Path-Delay Degradation

With the down-scaling of mainstream process node in modern semiconductor industry, the effective electric field of transistors and the on-chip temperature are getting higher, which has lead to more serious aging effects in standard cells. The aging caused device degradation leads to increased path-delay and in turn timing issues in integrated circuits. To meet the demands for high reliability systems, integrated circuit designers have to find methods in design stage to avoid such timing issues. In this case, prediction of aging caused timing degradation becomes a key prerequisite for implementing this task. In this work, a machine learning based predictor is illustrated for an accurate and efficient solution to predicting the path-delay degradation caused by aging. Within 60 seconds, this predictor can process 2,000 paths and the prediction precision (expressed as normalized root mean square error) between predicted values and simulated values is 7%. This result shows a promising application potential of the machine learning based predictor in critical path selection, aging timing analysis, and so on.