Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype

This paper presents an ASIC test chip designed and fabricated in
$0.35\ \mu\mathrm{m}$
CMOS process to further confirm and evaluate the advantages of the time-to-digital converter (TDC) based on a self-timed ring oscillator (STRO). Three TDCs with different number of STRO stages have been included in this test chip. Most of the measurements are perfectly in accordance with our theoretical claims. The fabricated circuits prove the ability of the proposed TDC architecture to enhance the time resolution by increasing the number of stages. Indeed, three TDCs with
$L=9,23$
and 61 have been integrated in the same chip. A 10-bit counter was used to cover a dynamic range of
$1.7\ \mu\mathrm{s}$
. The smallest TDC, with
$L=9$
, samples the time intervals with a time resolution of 72.5 ps, while a time resolution of 13.9 ps is obtained with the TDC of
$L=61$
.