Compact Bit-Parallel Systolic Multiplier Over GF(2m)

This article presents a compact and efficient bit-parallel systolic array structure for multiplication over the extended binary field, GF(2
$^{m}$
). The systolic array has a regular arrangement with local connections, making it more suitable for VLSI implementations. Also, it has the merits of having hardware complexity of order
$\mathcal{O}(m)$
that distinguishes it from the previously reported bit-parallel designs having hardware complexity of order
$\mathcal{O}(m^{2})$
. The achieved results exhibited that the suggested parallel architecture realizes a significant reduction in hardware complexity and the area-delay complexity over the competitor architectures previously published in the literature. Therefore, it is more suitable for usage in constrained hardware environments, having more restrictions on space, such as portable devices and smart cards.