Power Supply Noise Aware Physical Design with Decoupling Capacitance Allocation in System-on-Chip

Reduction of switching noise is a challenging task in integrated circuit design. The supply noise occurs in the pad locations due to inductive effect, resistive loss occurs due to electrical wiring on the chip and is also an effect of high switching activity of the transistors. This variation in voltage in the various electrical nodes may result in functional failure of the integrated circuit. Use of decoupling capacitors is a commonly used technique to reduce the power supply noise. Estimation and placement of decoupling capacitors is a difficult task in the design process. Thus a lot of effort has to be given in the latter stages to improve the overall performance of the integrated circuit. This article presents computer aided design approach to estimate decoupling capacitor and placement at the physical design stage to reduce the power supply noise. The main focus of this work is on allocation of decoupling capacitors so as to reduce the supply noise and also to keep cross-sectional area at its best after allocation of decoupling capacitor. Simulation results shows the overall design parameters are also satisfactory. This technique can also be used in other system-on-chip design.