Architecture Study for a Bare-Metal Direct Conversion Radar FPGA Testbench

As high-bandwidth all-digital radar platforms become increasingly prevalent, new signal processing techniques need to be explored to handle real-time processing of high-bandwidth data streams. The high bandwidth data streams produced by direct-sampling architectures present particularly difficult implementation requirements. To validate DSP algorithms for direct-conversion architectures with real measurements, testbenches need to be constructed with significantly different requirements than in other RF applications such as communication systems. One common usage of the term "testbenches" refers to pieces of code used during FPGA or ASIC simulation that employ specific clocks, interfacing to other devices, data input/output, etc. to validate an FPGA design. In this paper, a hardware testbench is discussed with a goal of providing the framework necessary to validate the design of DSP algorithms. Consequently, a modular radar signal processing testbench architecture is provided, including selected key implementation details and challenges. In brief, this paper's technical contribution is a system architecture for a high-bandwidth radar testbench, and its results section provides the resource utilization and floorplanning for a Virtex 7 FPGA.