Design and Implementation of Low power FinFET based Compressor

Compressors are the essential supplements of Full adders and half adder in any multiplier design. Compressors play a vital role in reducing delay and increasing the overall performance of a multiplier. In this paper, various compressors such as 5:3, 10:4, 15:4 and 20:5 are designed and implemented in Cadence virtuoso tool at 180nm technology. Later on, the compressor was designed using FinFET technology. The designs in both technologies were simulated, and their performance was compared. Simulation analysis depicts that the compressor designed in FinFET technology will show less power consumption than CMOS technology.