Analysis of 16-Bit and 32-Bit RISC Processors

The reduced instruction set computer, or RISC, is a microprocessor that executes small and similar instructions that execute in about similar time. The objective is to reduce the complexity of instructions which in turn reduces the cost, cycle time and the operating power. Though the 16-bit RISC has been around since 1970s, it has not been up to the mark and has posed a significant number of technical barriers. This was the very reason for the development of 32-bit and 64-bit RISC processors and the concept of pipelining. In this paper, our objective is to study behavioral model of 16-bit and 32-bit RISC processor and their independent instruction sets. The 16- bit RISC processor is a non-pipelined Harvard architecture-based CPU having separate data memory and instruction memory. The 32-bit RISC is a pipelined processor borrowing its implementation strategies from MIPS architecture. The processors include GPRs (General Purpose Register) and Flag registers (Carry, Zero etc.). The model discussed will simulate optimized Multiplier algorithm and will try to optimize the data path since Arithmetic and Logical operations consume more power along with high execution delay. The paper aims to draw a comparative study between the models based on their instruction sets and performance elements such as speedup, power dissipated etc. The individual models have been designed and simulated and have been finally integrated in a top-level module via XILINX ISE Design suit 14.7 along with power analysis.