An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique

This paper presents an 8-bit 1.25 GS/s folding-subrange ADC, implemented in 65nm CMOS technology. We design a coarse comparator to relieve critical metastability issue. A latch sharing technique in fine comparator can further reduce area overhead. Operating at 1.25 GHz sampling rate with low input frequency, the measured SFDR and SNDR are 56.5 dB and 43.4 dB, respectively. When split-then-share buffer turns on, ERBW achieves up to 2.5 GHz within ±1 dB bandwidth flatness. Peak DNL and INL are 0.71LSB and 0.72LSB, respectively. Setting at error magnitude of 4LSB and 32LSB, the bit error rate (BER) can achieve 5.4×10
^-6
and 5×10
^-10
errors/conversion, respectively. The ADC core consumes 20mW at 1.2V supply and occupies an active area of 0.14mm
²
.