VDPred: Predicting Voltage Droop for Power-Effient 3D Multi-core Processor Design

Modern applications present rapid, time-varying demands to the power supply systems. Designing for worst-case voltage droop leads to inefficient operations. These inefficiencies are amplified in 3D multi-core processors. Minimizing this voltage variation is key to improving power efficiency. One widely accepted method is to apply droop compensation into the voltage regulators. However, as the design complexity rises, the response time of the droop compensation fails to keep pace with the speed of load current switching in the modern processors. In this paper, we propose VDPred, a droop prediction system integrated with a reactive control loop inside a typical on-chip buck regulator of the 3D processor. VDPred predicts and eliminates voltage droops that produce worst-case operating voltage margins. It constructs an offline learning model for power prediction based on the pipeline and cache microarchitectural events. When VDPred predicts a hazardous droop, the circuitry warms up the regulator and pulls up the supply voltage against a voltage loss before the droop happens. VDPred can deal with very fast droop events, on the order of nanoseconds, and thus the voltage guard-band and power consumption of the processor can be further reduced compared to existing state-of-the-art techniques. We evaluate VDPred in both single- and four-core configurations of a 3D processor with the cycle-accurate full-system simulator. Results show a significant reduction in voltage guard-band and up to 7% runtime power of the overall system.