A Compact Model for Relaxation Effect in Analog RRAM for Computation-in-Memory System Design and Benchmark

Analog RRAM is considered as a promising emerging device for the future computation-in-memory system. However, the relaxation effect shows significant impact on system performance. It causes high accuracy loss for inference application. In this work, we have statistically studied the relaxation effect of analog RRAM. Based on the statistical measurement results, a compact model for relaxation is established. The simulation results can match experiment results well for different conductance levels at different relaxation time. Furthermore, a device-level to system-level simulation framework is proposed. The simulation framework supports both inference and on-chip training, and the compact relaxation model is embedded to the framework to benchmark the CIM system. Finally, a suppression method is further provided for relaxation effect from system level.