A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO

An all-digital phase-locked loop (ADPLL) with adaptive higher-order filter is proposed in this paper. The proposed ADPLL can select the first to third order of the loop filter by turning the IIR filter to adjust the system performance and attenuate input noise. Moreover, the phenomenon that spurious tone is getting closer to the main tone at higher-order ADPLL will be analyzed in this paper. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. The total area of the ADPLL core is 0.0106 mm2. By turning on the IIR filter, the measured rms jitter is 0.6 ps (0.298 % UI) and the power consumption is 5.1 mW from a 0.9 V supply at 4.96 GHz output frequency with 40 MHz reference clock.