Design and Implementation of High-speed Low Voltage 4x4 Vedic Convolutor

Digital signal processors involve different operations to compute problems, convolution being one of the most important and fundamental among them. This paper proposes a CMOS-based linear, discrete convolutor system designed to increase speed of operation at a considerably low voltage level. Vedic multipliers formulated on the basis of Urdhva-Tiryagbhyam Sutra have been used as sole multiplication method at all levels of computation. Carry Look-ahead Adders (CLAs) have been employed as the chief methodology of addition. This amalgamation of Vedic multipliers and CLAs helps to curtail propagation delay values to bring about faster calculation. Moreover, power-delay product or PDP is found to be greatly lessened in this arrangement of a high-speed, low voltage convolutor structure simulated using 22nm CMOS technology. A thorough evaluation of the proposed architecture has been laid out in this paper.