Area efficient VLSI architecture for reversible radix_2 FFT algorithm

In this work, we propose a new way of implementing Fast Fourier transform multiplier. Previous approaches achieve FFTs with a unity gain using a complex multiplier or a non-unity gain factor. The IEEE 754 format is used for a floating-point number representation. This project proposes an effective float reconstruction scheme that showed greater delay and area implementation. A community of Karatsuba and Urdhva-Tiryagbhyam algorithms are used to implement a binary multiplier. The algorithms are implemented by Verilog (HDL) and are targeted to the Xilinx ISE simulator for FPGA Spartan-3E board. This decreases the FFT architecture and design computing resources.