Analysis of the Programmable Soft IP-cores Implementation for FPGAs

Soft programmable IP-cores are usually used to speed up the integrated circuits design in FPGA. Soft blocks are formed from programmable logical FPGA elements independently from specific location on the FPGA and do not have pre-routed paths. Some FPGA architectures contain specialized resources to improve IP-cores design efficiency. It is necessary to consider these resources in CAD methods and components development.The paper presents the comparative analysis of two types of soft IP-cores implementation. The first type utilizes the architectural features of the FPGA due to a special block library. The second one obtains the results of automatic synthesis in a standard elements basis. The final size of designed IP-cores and the amount of utilized routing resources are compared. Also, the paper describes the specifics of the FPGA routing resources usage and the other implementation issues of such soft IP-cores as an n-bit adder / subtractor, an up-to-N counter, and a shift register.