Hardware Implementation of Single-carrier Time-domain Turbo Equalization for Severe Multipath Acoustic Communication Channels

This paper proposes a low-latency FPGA implementation for Turbo equalization to combat very long multipath fading channels where the Intersymbol-interference (ISI) channel length is on the order of 100 taps. Turbo equalization is essential for such severe multipath channels, but exhibits very large latency and high computational complexity due to its sequential and iterative data processing on large-scale matrix arithmetic. This paper proposes an FPGA acceleration architecture to exploit the Hermitian symmetric property of the channel Gram matrix and convolutional nature of Sequential Interference Cancellation (SIC), and successfully implements a linear Turbo equalizer of 100 taps on a Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. The architecture is able to support two turbo iterations for a 1024-symbol block size and achieve 200 kilo-symbols-per-second (ksps) transmission rate.