Comprehensive Design Methodology of Switch Stack in Pulsed Power Supply for EML

This article presents a comprehensive methodology for designing a fully protected efficient semiconductor switch stack for electromagnetic launchers (EMLs), using commercially available thyristors and diodes by developing behavioral (Verilog-A) models of the switches accounting for their nonidealities. The appropriate values of protection components are obtained through SPICE simulations. Using ABB thyristors and diodes, a design-example of a 400-kJ pulse-forming network (PFN) with rated peak voltage and peak current of 11 kV and 135 kA, respectively, is presented. The simulated peaks of dv/dt and di/dt of the main switch are found to be well within the maximum permissible limits, 40% and 10% respectively, for a turn-on timing skew of 1 μs between the thyristors. The addition of the protection components reduces the efficiency ( η) of the PFN by 3.5%, thus indicating that proper designing of the protection components does not decrease the efficiency of the PFN significantly. The second example of a 100-kJ PFN using off-the-shelf Infineon switches is also presented to clarify the proposed methodology.