Finite Element Stress Analysis of thermal stress Failure in a Novel Chip Embedded Integration Package

In this paper, the thermal stress problem in a novel chip embedded integration package is analyzed by finite element method. A novel chip embedded integration package can improve system integration level. In this kind of package, chip is embedded in a cavity of silicon substrate, benzocyclobutene (BCB) is filled in the gap space between the chip and silicon substrate. As the thermal expansion coefficients of the three parts (BCB\substrate\chip) are different, internal stress will occur in the package. The research focuses on the effect of characteristic size on package stress. Through finite element simulation and parametric design of package structure size, we can obtain detail stress cloud diagram of package. Then, we can make two conclusions through the simulation result and stress cloud diagram. First, the fail point is located in the benzocyclobutene that fills the gap between the chip and substrate cavity. Second, the stress of benzocyclobutene is affected by substrate cavity size and chip size. There is an optimal matching relation between these feature sizes, which can minimize the stress in benzocyclobutene. Through simulation optimization, the best package size matching relationship can be obtained. The optimized results were confirmed by analysis and comparison of simulation results and experiments. The research achievement can be used to optimize the reliability of similar packages.