A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process

A 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with 20dB loss compensation is proposed in a 65nm CMOS technology. The receiver employs a quad-rate hybrid DFE architecture to reduce power consumption. DFE can halve the number of summers by adding reset to slicer, and multiplexer to the summer. In the proposed DFE, 7Gb/s data converted to digital signals by the slicer and IIR filter are added at the summer, and d flip flop sends a signal that the noise has been removed to the output. Because slicer and summer are implemented to operate at high speed, the proposed DFE doesn't require the sample-and-hold (S/H). So, the DFE has a simple structure and operates at high speed with low power consumption. The proposed DFE occupies 0.023mm
²
and power consumption is 18.2mW with 1.2V supply voltage.