A PLL Synthesizer for 5G mmW Transceiver

The paper presents a 24.4 to 26.8 GHz PLL for 5G mmW transceivers in CMOS 65nm process. An integrated voltage-controlled oscillator (VCO) and a set of high-speed dividers are used to accomplish all the frequencies. The charge pump circuit is utilized to achieve good up/down current matching. The PLL can be locked from 24.4 to 26.8 GHz, which consumes a power of 33 mW at 1 V power supply. The phase noise of the PLL is -114dBc/Hz at 10 MHz offset, while it is locked at 24.6 GHz. The PLL occupies a chip area of 0.85 mm
²
.