Advanced On-Chip Variation in Static Timing Analysis for Deep Submicron Regime

As technology scales into the deep submicron regime, On-Chip Variation (OCV) has become a dominant factor which influences the performance and yield of the circuits. Considering OCV analysis in Static Timing Analysis (STA) tools is therefore one of the most crucial issues in VLSI designs nowadays. Advanced OCV (AOCV) technique is widely deployed in industry to account for OCV effects at smaller geometries. In this paper, the first incremental AOCV methodology is proposed to implement variation parameters for On-Chip deep submicron. This approach has been implemented in an industrial place-and-route tool with high speed design consisting of data and clock paths. The experimental results on industrial designs show that the optimization flow of path-based AOCV technique can significantly reduce the pessimism and improve the final Quality of Results (QoR) compared to the traditional OCV. Specifically, evaluation results show that the proposed AOCV model has over 30 % with clock only and 25 % with clock and data lesser than the traditional OCV in total violation paths. Furthermore, the proposed AOCV model also performs about 37% with clock only and 26 % with clock and data lesser than the traditional OCV in total violation endpoints.