A Charge Pump Phase-Locked Loop with Fast Locking Mechanism for FPGA in 28nm CMOS Technology

Phase-locked loop has been widely applied in FPGA, which is used to provide high-quality clock. In this paper, a charge pump phase-locked loop with a new fast locking mechanism embedded in Field Programmable Gate Array is proposed. Based on the traditional structure of PLL, some new modules are added to reduce the locking time, involving a VCO frequency detection module, a pre-charge module and a configurable filter. The simulation results show that this structure can effectively reduce the locking time of the PLL.