A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic

This paper presents a 2MS/ s 12-bit SAR ADC with RC two-step scheme. The SAR ADC has trade-off between size and high-resolution specification. The capacitor array has size problem because total capacitance of capacitor array increases exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used the resistor array with the capacitor array. Also, the proposed SAR ADC applied different bit-cycling time for each bit. A prototype ADC was implemented in a 28-nm CMOS technology. The chip consumes 221μW under a 1.0-V supply. The ADC core occupies an active area of 0.02mm × 0.79mm.