A 3.2–3.6GHz SOI-LDMOS Dual-Input Doherty Power Amplifier

This work presents a SOI-LDMOS Dual-Input Doherty Power Amplifier (DPA). The proposed DPA is implemented in a 130nm SOI-CMOS technology and packaged using flip-chip on a laminate substrate. Low DPA combiner loss is achieved using high-Q inductors embedded onto the laminate. The proposed Doherty PA exhibits a measured peak output power of 30 dBm at 3.2GHz, under 3.4V voltage supply. The peak Power-Added Efficiency (PAE) is 40%, and PAE at 27dBm output power is 37%. With a 10MHz LTE signal, the linearized DPA achieves a measured ACLR of -42 dBc at 27dBm output power.