Impact of interface layer on charge trapping in Si:HfO2 based FeFET

The impact of interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperature, the FeFET with metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electrontrapping dominated PBTI (i.e. ΔV
_t
> 0), whereas at room temperature, negative threshold voltage shifts (ΔV
_t
) are observed. We demonstrate a link between interface layer and the subsequently-deposited ferroelectric layers effective permittivity: higher permittivity, consistent with higher tetragonal phase/ lower orthorhombic phase content is seen when the ferroelectric layer is deposited on hydrogen terminated silicon, whereas anomalous BTI consistent with higher orthorhombic phase is observed when the ferroelectric is deposited on oxygen-rich (SiO
₂
, SiON) surfaces.