Research of Power Loop Layout and Parasitic Inductance in GaN Transistor Implementation

Power loop is critical in the PCB layout consideration. Especially for high frequency GaN transistor applications, a low inductance power loop design is needed to guarantee the switching reliability and the operation efficiency. Finite element analysis is generally used in the power loop inductance quantification, which is time consuming and impractical for parameters sweep. In this article, a numerical equation for power loop inductance estimation is given based on the novel loop inductance model. The power loop inductance can be estimated in a fast approximation approach. Three different layout methods are compared in regard to power loop inductance and thermal performance. A modular buck converter prototype is designed to demonstrate the effectiveness of the given numerical equation for power loop inductance estimation. The pros and cons of each layout method in the practical applications are discussed.