Radar Solder Joint Monitoring Technology Based on Circuit Modeling and Simulation Technology

The demand for life-cycle management of weapons and equipment drives the research and development of radar fault prognostic and Health Management (PHM) technology. With the continuous development of information technology, digital circuits account for more and more of the radar due to their excellent reliability and stability. The digital circuit will be affected by the surrounding environmental stress (thermal stress and mechanical stress) in the process of use, which will cause deformation of printed circuit board and lead to the failure of the pin of the chip, and ultimately lead to the failure of the chip, which may lead to serious damage to the radar. The Field Programmable Gate Array (FPGA) chip, due to its Programmable characteristics and its important position in the digital circuit, we regard the monitoring of FPGA pin as the standard to judge whether the digital circuit communicates normally. In this paper, the damage of FPGA pin is monitored by means of solder joint-built in self test(sj-bist) and the monitoring circuit is designed by means of principle analysis and IP core design, and the monitoring results are analyzed quantitatively by circuit design. The simulation experiment is carried out by PSpice simulation software, and the feasibility of monitoring circuit design by sj-bist method is verified by circuit construction and simulation analysis. Finally, the influence of temperature and internal resistance on the monitoring accuracy is obtained through simulation experiment, and the monitoring results are modified through theoretical analysis to improve the monitoring accuracy of the sj-bist technology.