Fabrication and Characterization of A Novel Fully Self-Aligned Split-Gate Sonos Memory Device

A novel low-power fully self-aligned split-gate silicon-oxide-nitride-oxide-silicon (SONOS) flash memory with “memory-last” configuration has been fabricated for the first time at 90-nm node. Firstly, the fabrication sequence is introduced. Then, the operations of unit cell are presented and the transfer characteristics are also experimentally demonstrated. It was revealed that, a wider V
_TH
window can be obtained in the memory gate (MG) transistor, although it exhibits a slightly small V
_TH
. However, V
_TH
of selected gate (SG-) transistor is still too large for low-power applications. This is ascribed to the inappropriate source line (SL-) halo, arsenic implantations, and thermal budget, which induces a high threshold voltage locally at SL-side. However, it still proved that this novel split-gate SONOS memory is very promising for low-power applications.