Timing Violation as Dominant Reason for Failure of Clocked Digital Circuit Due to RF Interference in Supply

This paper covers our observations of the failure behavior of a clocked digital circuit with sinusoidal interference acting on its supply. Conventionally, it has been thought that interference causes mainly logic-level errors in digital circuits, with the average value of the interference determining the circuit delay. As the interference cycle time is much shorter than both the data path delay and clock cycle time, the average value of the interference is almost zero. However, it still causes a timing violation, rather than a logic-level error, in the circuit. This observation was at odds with conventional thinking. This behavior was confirmed with both transistor-level simulations and board-based measurements. The findings of the present study are important for determining the frequency response of the maximum tolerable interference amplitude of a digital circuit in the design phase.

Introduction

The large-scale use of radio, the large-scale increase and intensive placement of electronic equipment and components, harsh environment, and intentional electromagnetic attacks, etc., all of these will lead to electromagnetic interference waves at the power, signal or other locations of integrated circuits. These electromagnetic waves will have a certain negative impact on the stable working state of the digital circuit. So the electromagnetic immunity of integrated circuits (ICs) has been a focus of concern for a considerable time.