Instrumentation and Extension of reduced, simulated Single Cycle MIPS architecture to improve Student Comprehension

This Innovative Practice Work in Progress Paper presents results of efforts to improve student comprehension of computer architecture. Students majoring in Computer Science at the United States Air Force Academy (USAFA) are typically enrolled in the department's Computer Architecture course during the spring of their sophomore year. These students traditionally struggled to understand exactly what was occurring in the Central Processing Unit (CPU) of a computer and demonstrated poor performance on assignments, tests, and the final exam regarding how these components are used in a processor. Other institutions have had success giving their students a series of assignments which culminate in their implementing a complete CPU architecture in a logic simulator. However, this fairly time consuming assignment was not deemed feasible at USAFA where student time is divided between various required duties, academics, and athletics. Instead, a reduced version of the MIPS (Microprocessor without Interlocked Pipelined Stages) single cycle architecture (SCA) as described in Harris and Harris was implemented in Logisim and provided to the students. The students then modified the given circuit to support additional instructions and added logic probes to observe internal values. They then ran assembly language code containing the new instructions through the augmented architecture. Throughout each step, the students could observe the processor's behavior using the previously installed probes, which substantially increased their understanding. The improvements in performance on the CPU questions have been significant and lasting. These results are especially noteworthy due to the minor additional work the students had to perform to increase their understanding.