Adaptive Methodology for Process-Voltage-Temperature Verification

In pre-silicon verification of integrated circuits the Process-Voltage-Temperature coverage is typically done through a grid in the Voltage-Temperature space and Monte Carlo sampling of the Process space. The main limitations of this approach are the low coverage in the Voltage Temperature space and the high number of the required simulations. This paper proposes a circuit verification methodology that distributes the experiments in such a way that more experiments are concentrated in regions where the electrical parameter is outside or close to the specification limit. This is achieved by modeling the dependency of electrical parameters on the Process-Voltage-Temperature variables. The predictions of the model are then used to determine the new samples to be simulated, encouraging the ones that are expected to exceed the specification limit. We compare our results with a traditional Monte Carlo grid approach and evaluate both methods on an industrial benchmark circuit (a voltage regulator). The experimental results show that we obtain at least the same coverage while reducing the total number of simulations by 77%.