Fault localization of IDDQ failure using External trigger Synchronous LIT technique

This paper describes a new LIT technique named External trigger Synchronous LIT (ESLIT). LIT is widely used in device analysis from initial investigation to fault isolation. This technique uses a “lock-in function” to reduce thermal spreading from the heat source. Conventional LIT analysis is usually performed under limited set-up conditions with some probes without ATE. However, in the case of ESLIT, ATE can be used to reproduce the failure state of the DUT during the LIT analysis. And the “lock-in function” is used to identify specific hotspots that correspond to IDDQ failure states. In our experiment, the results of ESLIT perfectly agreed with IDDQ fault diagnosis candidates. On the other hand, PEM and OBIRCH detected not only logic-related points, but also non-logic-related points that did not match the fault diagnostic results. We also confirmed that ESLIT is available nondestructively. We think that ESLIT is a useful technique for IDDQ failure analysis since it can identify the true root cause even in the case of multiple failure.