A 4K Josephson memory

The authors describe the design and experimental performance of a 4 K*1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlO/sub x//Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW.<
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