Variation-Tolerant Digital Circuit Design for Printed/Flexible Electronics (Invited Paper)

Contemporary digital circuits are synchronous-logic and are operationally error-free because they are designed to complete their operation within a predefined time period. In some applications, such as the MOST operating in ultra-deep subthreshold or in flexible electronics where the TFT is printed, the ensuing operation of digital circuits is prone to error. This is because the variations of the delay of the transistor are very high and the ensuing predefined time period is difficult to ascertain. In the case of the printed TFT where its substrate is flexible and hence possibly bent, the delay is possibly intractable, in part because the profile of the bending may not be known. In this paper, we will discuss the commonality between ultra-deep subthreshold and printed TFTs in terms of their variations. We describe the application of the esoteric asynchronous-logic Quasi-Delay-Insensitive (QDI) signaling protocol to design digital circuits that innately accommodate intractable delay characteristics, i.e., error-free operation despite intractable variations. To mitigate the hardware, power and timing overheads of QDI, we will present our proposed modified signaling protocol named Pseudo-QDI and our proposed Pre-Charged-Static-Logic design style.