Functional Verification closure using Optimal Test scenarios for Digital designs

The ever-increasing design complexity of Integrated Circuits (ICs) resulted in challenging aspects of functional/logic verification, in terms of verification platform complexity, achieving verification goals like code/functional coverage and unbounded verification time/efforts for any given digital design. Currently, Functional Verification closure depends on CAD/EDA tool Random Seed capability combined with constrained random verification methodology like Universal Verification methodology (UVM) to generate exhaustive test scenarios, thereby achieving coverage goals for test regressions. In this paper, a framework is proposed for generating optimal test scenarios by interleaving design under test (DUT), input stimuli solution space, constrained random solution space and required levels of test stimuli combinations.