Effect of the accumulated plastic deformation on J-integral for TSV-Cu/SiO2 interface crack under cyclic thermal load

Through-Silicon-Via (TSV) is a crucial technique developed for 3D integrated circuits (3D ICs), which enables to improve device performance and allows for heterogeneous integration schemes. However, the mismatch of coefficient of thermal expansion (CTE) between TSV-Cu and Silicon (Si) substrate leads to the cracking behvaiors easily, especially, when cyclic thermal loading exists during the cycling of different processes. Correspondingly, the plastic deformation occurs during the thermal cycling, which could lead to the formation of plastic deformation such as residual stress and residual strain along the interfaces between TSV-Cu and Si substrate as well as interface between Cu and the dielectrics (e.g., SiO
₂
). Cracks can be formed between those interfaces, which generates reliability issues. Hence, the purpose of this paper is to study the effect of the cyclic plastic deformation on the J-integral for TSV structure during cyclic thermal loading. 2D FE models of TSV structure are constructed to perform the numerical analysis, in which a crack is embedded in the TSV-Cu/SiO
₂
interface. A novel numerical method is developed to compute J-integral for TSV-Cu/SiO
₂
interface crack under cyclic thermal load. The effect of the cyclic plastic deformation on J-integral for TSV structure are presented.