New Strained LDMOS With Ultralow ON-Resistance by Si1−yCy Source Stressor for About 20 V Low-Voltage Applications

A novel low ON-resistance strained lateral double-diffused MOSFET (LDMOS) with silicon-carbon (Si
_1-y
C
_y
) source is proposed for low-voltage applications. Due to the lattice mismatch between silicon and Si
_1-y
C
_y
, the source-side Si
_1-y
C
_y
stressor introduces the lateral tensile stress and vertical compressive stress along the conduction path to enhance the electron mobility in the channel and drift regions and hence improves the ON-state characteristics. As the stress relaxation in the drift region, the strain-induced breakdown voltage (BV) deterioration can be neglected. The simulation results show that the ON-resistance (R
_on
) of the proposed device is decreased by 19.2% compared with the conventional LDMOS without strain at a gate overdrive voltage (V
_GS
-V
_T
) of 1 V. At the same time, the novel LDMOS achieves 47% and 28.8% increment in the drive current (I
_D,sat
) and peak transconductance (G
_m,peak
), respectively, while keeping a nearly identical BV of 23.08 V. Besides, the improved cutoff frequency (f
_T
) and transconductance-to-current-ratio (G
_m
/I
_D
) are also obtained in the novel LDMOS.