Analysis of Gate-Metal Resistance in CMOS-Compatible RF GaN HEMTs

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and
${f}_{\text {MAX}}$
of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process leads to
${f}_{\text {MAX}}$
enhancement up to ~50% for devices scaled down to 0.32-
$\mu \text{m}$
gate lengths. The gate resistance for the T-shaped gate is modeled from the S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and the parasitic capacitance in GaN HEMTs is highlighted in this case.