An Efficient Implementation of Radix-4 Integer Division Using Scaling

This paper presents the design of a radix-4, 32-bit integer divider that uses a recursive, non-restoring division algorithm. The primary focus for this design is on high-speed operation while maintaining low power consumption. In addition, scaling is utilized within the quotient-selection table to reduce the size of the quotient selection. This implementation accepts 32-bit unsigned integers as input, and returns the quotient, remainder, and a special case divide-by-zero flag. Estimates for area, delay, and power consumption are given for this design implemented in IBM/GF 32nm SOI technology. Moreover, gated registers are utilized to reduce the energy footprint. The results are compared to similar Synopsys DesignWare dividers.